The present invention relates to information processing systems including multiple processing devices linked to multiple memory cards of main storage through a shared interface, and more particularly to means for inserting and extracting tag bits from data stored in main memory with minimal interaction of the processors with main storage through the interface.
In recent years, the performance of information in processing devices has improved considerably, particularly terms of more rapid performance of data processing operations. Information processing networks increasingly employ multiple processing devices sharing a common interface for transmitting data between the processors and main storage, which typically is composed of multiple memory cards. Improvements in memory subsystems have not kept pace with improvements in processors, particularly when multiple, parallel processors are used in the network. Accordingly, system or network architectures have been modified to compensate for a main storage which operates relatively slowly as compared to the processing devices. Cache memories and other techniques have been employed, in an attempt to uncouple the processors from the memory cards in main storage.
In certain information handling systems it is desired to identify some of the data words as "pointers", which contain, along with other bits, an address identifying a particular byte or number of bytes within a memory, in a particular main storage. To enhance system performance, it is advantageous to store pointers and other data words mixed, i.e. without reserving particular areas in main storage for exclusive storage of pointers. However, since a pointer in one area of main storage may be used to gain access to data in another area, the capability of checking the integrity of pointers is essential.
To this end, a hardware tag can be provided for each word in main storage. As disclosed in U.S. Pat. No. 4,241,396 (Mitchell et al), each pointer is a "quad" word having sixteen bytes, with each of the four words having a tag bit. The pointer is considered tagged (i.e. valid as a pointer) when all four hardware tag bits are set, and untagged when any of the tag bits is reset. The tag bits can be set only by tag instructions. All other instructions reset the tag bits. Thus, if a pointer is inadvertently modified by a data handling instruction rather than a tag instruction, the reset tag bits identify the pointer as not valid.
A number of modifications have been proposed to this system. For example, IBM Technical Disclosure Bulletin, Vol. 24, No. 10 (March 1982) relates to an improved pointer verification scheme involving accumulating all tag bits of the quad word, rather than checking the tag bit latches every eight bytes. IBM Technical Disclosure Bulletin, Vol. 25, No. 2 (July 1982) discloses storage of tag bits in a separate memory, apart from main storage. Quad words thus stored are said to be more compatible with conventional data word size formats, and the need to separate tag bits from data before writing the tag bits on a disc is eliminated. For most effective use of memory, active tag bits are stored in a high performance memory, with non-active tag bits provided to main storage.
It is advantageous to provide pointers in a format which permits mixed storage with other data in main storage, yet also desirable to store data in auxiliary devices, perhaps in formats which do not allow tag bits within data words. Thus, there is a need to modify the tag bits in data words transmitted between main storage and this type of auxiliary storage.
More particularly, data often is moved in page or multi-page lengths, with each page including, e.g. 512 bytes. Pointers and other data words are mixed in main storage, with the pointers identified individually by their associated tag bits. When a page of data is moved from main storage to auxiliary storage, however, the tag bits are extracted, i.e. accumulated and saved in a separate field as part of the page header which is moved into the auxiliary storage device first, followed by data. Conversely, when a page of data is moved from auxiliary storage to main storage, tag bits are reinserted into the appropriate tag bit locations.
These tag bit functions traditionally are carried out by the processor or processors, interacting with main storage through a bus or other interface between the processors and main storage. Tag extraction and insertion functions thus require considerable processor time and memory bus overhead, and require repeated access to the memory arrays in main storage, all to the detriment of network performance.
Therefore, it is an object of the present invention to provide a data processing system in which tag bits associated with address pointers in main storage can be extracted and reinserted, with substantially reduced use of the interface between main storage and multiple processors.
Another object of the invention is to transfer some of the intelligence involved in tag bit modifying operations from the processors to the memory cards of main storage.
A further object is to increase the speed at which tag modifying functions are performed.
Yet another object is to provide a data processing network in which the insertion of tag bits or other indicia into data words is accomplished with just one access to the arrays of main storage.